1. Field of the Invention
The present invention relates to a hard macro cell and a semiconductor integrated circuit using the hard macro cell and, more specifically, to a hard macro cell which is incorporated into a semiconductor integrated circuit as a functional block that is a circuit for performing a predetermined function, such as that of a RAM or a ROM.
2. Description of the Related Art
A semiconductor integrated circuit is generally composed of a plurality of functional blocks. Among these functional blocks, ones having a variety of uses, such as memory blocks, are generally treated as libraries at the functional block level so that they can be used in various applications. Such functional blocks treated as libraries are referred to as hard macro cells. Aside from the hard macro cells, the functional blocks include soft macro cells, in which design content can be modified as is appropriate when the semiconductor integrated circuit is designed. As shown in FIG. 8, the semiconductor integrated circuit is typically formed by combining a plurality of functional blocks including the hard macro cells and the soft macro cells.
In recent years, mainly system LSIs onto which many large-sized hard macro cells are loaded have been used as the semiconductor integrated circuits. The size of the hard macro cells is not uncommonly 5×5 mm or greater, and the size of the LSI is generally 10×10 mm or greater.
Thus, there has been a problem in that global wires for mutually connecting the hard macro cells have been lengthened in proportion to the size of the LSI, which has resulted in increased signal delay between the wires.
Further, because voltage at a power supply for the LSI has been decreased due to advances in fine patterning (reductions in design rules), noise resistance of signals needs to be improved. Not only overcoming the signal delay, but also improving the quality of signal waveforms are important problems.
In order to solve these problems, a repeater (cell) for adjusting the signal delay and the signal waveforms has conventionally been provided at an intermediate portion of the global wires, or the global wires have been passed through the hard macro cell so as to be shortened as much as possible.
FIG. 8 shows a conventional semiconductor integrated circuit 100 that includes functional blocks 101 to 107 for performing predetermined functions. A global wire 108 connecting the hard macro cell 103 (functional block 103) and the hard macro cell 105 (functional block 105) is formed so as to circumvent the hard macro cell 104 (functional block 104), and a repeater 109 is provided at an intermediate portion of the global wire 108.
In such a semiconductor integrated circuit, however, there has been a problem that signal delay and deterioration of signal waveforms cannot be effectively reduced because the global wire is disposed so as to circumvent the hard macro cell 104 and is thereby lengthened excessively. Alternatively, when the global wire is passed through the hard macro cell, there has been a problem that the hard macro cell may cause operational errors because the hard macro cells, such as RAMs or ROMs, which perform analog operations are easily affected by cross-talk with other signal wires and the like.
Japanese Patent Application Laid-Open No. 11-163268 discloses a semiconductor integrated circuit in which a buffer circuit for delay adjustment is provided in a functional block. In this application, however, there is a problem that circuits around the buffer circuit may be affected by cross-talk depending upon the position of the buffer circuit.